The processing of a semiconductor wafer is divided into various groups of steps normally referred to as: the front-end-of-the-line (FEOL); middle-of-the-line (MOL) and back-end-of-the-line (BEOL). One of the final steps at the BEOL in the wafer processing is applying a protective passivation layer on the entire wafer. The passivation step includes the deposition of a protective passivation layer over the integrated circuit (IC) device. The function of the passivation layer is mechanical, to protect the processed wafer from the environment during transportation, handling, and final packaging. An edge seal is a region between the active chip area and the dicing channel that is susceptible to moisture damage. Moisture damage can alter the electrical properties of the integrated circuitry of the individual IC chips on the wafer, thus leading to device failure. Eventually, passivation areas are removed forming dicing regions to allow dicing the wafer into individual IC chips.
When the BEOL is formed using organic insulators like polyimide formed on the silicon insulator surface, a difficulty arises when this polyimide passivation layer, peels (delaminates) or cracks at the edge seal region due to stress. During final wafer processing of the polyimide passivation layer, the layer is etched by a process such as reactive ion etching (RIE) to open terminal via (TV) pads over the metal landing pads and edge seal channel regions to the silicon insulator. The edge seal channels are exposed silicon insulator locations not covered with polyimide which will eventually be diced. Uncovered edge seal channels of the passivation layer become problematic. For example, an edge of a polyimide passivation layer etched by RIE may absorb up to 15 percent more moisture on its RIE etched edges; as compared with the bulk polyimide passivation regions. This causes the edges to swell and ultimately delaminate from the silicon insulator. As the edges delaminate, capillary-like separations are formed between the passivation layer and the silicon insulator, providing a site for moisture to aggregate, creating moisture-filled channels within the IC device. These channels allow ions to move freely about and hence are drawn into the active chip area, which inevitably leads to corrosion within the IC device and ultimately failure.
Heretofore, various methods have been proposed for protecting the etched edges of a passivation layer from delamination by peeling or cracking. For example, one method proposed application of a second polyimide layer over the edge of a first polyimide passivation layer etched by RIE. The second polyimide layer is then wet etched to reopen the channel as well as the TV pads. A disadvantage of this method is that it is (A) more time-consuming and, (B) expensive, and (C) impacts layout ground rules as it requires the use of an additional mask to perform the wet etch. Therefore, there exists a need for an improved passivation layer edge seal for an integrated circuit device.